Bonjour a tous
Je suis débutant et j’ai déjà un problème 
Sous CPU-Z ma ram est considéré comme de la 5300 alors que j ai acheté de la 6400.
Que dois je faire pour rectifier le tir
Merci
ps: voila les caractéristiques de la mémoire
Memory type: DDR2 SDRAM
Error correction: NONE
Voltage interface level: SSTL (1.8V)
Data width: 64 bits
Number of physical banks: 2 (double sided)
Number of logical banks: 4
Number of row addresses: 14 14
Number of col addresses: 10 10
Bank density: 512 512 MB
Primary RAM Width: 8 8 bits
Error checking RAM Width: 0 0 bits
Module density: 1024 MB
Refresh rate: 7812.500 us
Self-refresh: Oui
Burst lengths supported: 4 8
CAS 3.0:
Cycle time (tCYC) = 5.000 ns fMax = 200.000 Mhz
Access time (tAC) = 0.600 ns fMax = 1666.667 MHz
CAS 4.0:
Cycle time (tCYC) = 4.300 ns fMax = 232.558 Mhz
Access time (tAC) = 0.500 ns fMax = 2000.000 MHz
CAS 5.0:
Cycle time (tCYC) = 3.000 ns fMax = 333.333 Mhz
Access time (tAC) = 0.450 ns fMax = 2222.222 MHz
InconnuInconnuMin delay, Bk/Bk random cols: 0 clocks
Min row precharge time (tRP): 15.000 ns
Min row active delay (tRRD): 7.500 ns
Min RAS to CAS delay (tRCD): 15.000 ns
Min Actv to precharge (tRAS): 45.000 ns
Addr/Cmd setup time: 0.200 ns
Addr/Cmd hold time: 0.270 ns
Data setup time: 0.100 ns
Data hold time: 0.170 ns
Write recovery time (tWR) 15.000 ns
Int Wr to Rd Cmd Dly (tWTR) 7.500 ns
Int Rd to Pchg Cmd Dly (tRTP) 7.500 ns
Min Act/Auto-Rfrsh Time (tRC) 60.000 ns
Min Auto-Rfrsh/Act Cmd (tRFC) 105.000 ns
Max Dev Cycle time (tCK max) 8.000 ns
Max DQS-DQ Skew (tDQSQ max) 2.400 ns
Rd data hold skew Fctr (tQHS) 3.400 ns
PLL relock time 0.000 ns
Memory analysis probe chars: 00
DIMM type: UDIMM (module width = 133.35mm)
FET switch external enable: Non
Analysis probe installed: Non
Includes weak driver: Oui
Manufacturer’s JEDEC ID code: 00000000 0000987f
Module manufacturing location: 4 (manufacture dependant)
Module part number: 99C5316-019.A00LF
Module revision code: 0 (manufacture dependant)
Module manufacturing date: Wk 7 of 2008
Module serial number: 78cc1c8c
SPD revision: 1.1
Edité le 21/04/2008 à 21:00